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RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
RTL modeling with SystemVerilog for simulation and synthesis using SystemVerilog for ASIC and FPGA design
| Médium | Knihy Book |
| Vydané | 10. júna 2017 |
| ISBN13 | 9781546776345 |
| Vydavatelia | Sutherland HDL |
| Rozmery | 150 × 220 × 20 mm · 644 g |